This disclosure relates to mechanisms for deadlock avoidance support in network fabrics. In particular, this disclosure relates to mechanisms for deadlock avoidance support in Infiniband network fabrics, network on a chip (NoC) or a system on a chip (SoC).
InfiniBand (abbreviated IB), a computer-networking communications standard used in high-performance computing, features very high throughput and very low latency. Latency refers to a delay in packet delivery. InfiniBand is used for data interconnect both among and within computers. InfiniBand is also utilized as either a direct, or switched interconnect between servers and storage systems, as well as an interconnect between storage systems.
IB is a popular interconnect fabric architecture for High Performance Computing (HPC) systems. One of the main features of IB is the separation of network (switch/adapter) resources in independent virtual lanes that can be used for quality of service purposes. Several network topologies that are of interest in the HPC/Datacenter applications are vulnerable to deadlock (a complete cycle of dependencies between network resources that does not allow progress of traffic (e.g., packet delivery) anymore) and a general approach that is often used is to separate network resources into virtual channels and to enforce inside each switch a channel transition scheme that makes cycle occurrence impossible. Although already benefiting from independent resources (virtual lanes), IB switches have generally not offered support for such deadlock avoidance techniques and have been mostly used in the context of topologies that are intrinsically deadlock-free (such as fat tree topologies).
The increasing number of heterogeneous cores for general-purpose chip multiprocessors (CMP) and systems-on-chip (SoCs) leads to a complex variety of on-chip communication scenarios where multiple applications running simultaneously, trigger the exchange of various messages across processors, accelerators, cache memories, and memory controllers. Consequently, the next generation of networks-on-chip (NoC) should not only provide high performance and energy-efficient data delivery but also cooperate with the network interfaces of the embedded cores to meet special requirements such as message-class isolation and real-time data delivery.